1. Field of the Invention
The present invention relates to an insulated gate type semiconductor device that controls current by applying voltage to a gate electrode insulated from a semiconductor substrate and to a process for producing such a device. More specifically, the present invention relates to an insulated gate type semiconductor device capable of controlling large current with a high voltage resistance between an end portion of the gate electrode and the semiconductor substrate. The present invention also relates to a process for producing such a device, the manufacturing process providing a high yield and being simpler than know manufacturing processes.
2. Description of the Related Art
A semiconductor device (a power IC or the like) that is used in a power system for controlling large current by applying voltage to a digital circuit is primarily constituted by an IGBT (Insulated Gate Bipolar Transistor). This kind of semiconductor device generally has a structure as shown in FIG. 10. That is, a gate electrode 84 is formed on a semiconductor substrate 80, which is in contact with a source electrode 86. The semiconductor substrate 80 is provided with a known well structure such as a source diffusion portion 88 or the like. The pn-junction of the well structure prevents current from flowing in a direction of thickness of the gate electrode 84 if no voltage is applied thereto. The gate electrode 84 is insulated from the semiconductor substrate 80 with a gate insulation film 85. The gate electrode 84 is also insulated from the source electrode 86 with an interlayer insulation film 87. The semiconductor device of such a structure is called an insulated gate type semiconductor device. This kind of semiconductor device generally employs a layout wherein two elements are symmetrically arranged on left and right sides as shown in FIG. 10.
If a predetermined gate voltage is applied to the gate electrode 84 while a certain voltage is applied to the semiconductor substrate 80 in a direction of thickness thereof, a channel is formed in the semiconductor substrate 80, whereby current flows in a direction of thickness thereof. If the application of gate voltage is suspended, the current also stops flowing. In this manner, it is possible to control current by adjusting gate voltage. This operation substantially requires a voltage resistance of more than 30V between the gate electrode 84 and the semiconductor substrate 80.
A process for producing this kind of semiconductor device generally includes the steps of (a) sequentially forming the gate insulation film 85 and polycrystalline silicon on the entire surface of the semiconductor substrate 80, (b) subjecting the polycrystalline silicon to a patterning processing to form the gate electrode 84, (c) removing a portion of the gate insulation film 85 that is not covered with the gate electrode 84, (d) forming a well structure such as the source diffusion portion 88 and the like by means of ion implantation and an annealing process and (e) subsequently forming the interlayer insulation film 87 and the source electrode 86. In this manner, the semiconductor device as shown in FIG. 10 is obtained.
However, this semiconductor device has drawbacks, which will hereinafter be described. First, the semiconductor device cannot ensure a sufficient voltage resistance between the gate electrode 84 and the semiconductor substrate 80. This is because the gate insulation film 85 has a defect at an end portion of the gate electrode 84. That is, in removing the gate insulation film 85 (usually by means of wet chemical etching) in the aforementioned step (c), damage is caused to the portion of the gate insulation film 85 that is located under the end of the gate electrode 84, so that an undercut 90 as shown in an enlarged view of FIG. 11 is generated. Thereafter, the well structure is formed in the aforementioned step (d) and the interlayer insulation film 87 is formed (usually by Chemical Vapor Deposition method: CVD) in the aforementioned step (e). However, the undercut 90 remains as a void instead of being completely filled. This is partly because a sufficient amount of oxide layer cannot be formed in the undercut 90 due to an insufficient supply of oxygen in an intermediate step of thermal oxidation and partly because upon formation of the interlayer insulation film 87 by CVD, an entrance thereof is closed.
Hence, the oxide layer, effective in insulating the gate electrode 84 from the semiconductor substrate 80, does not have an enough thickness at the end portion of the gate electrode 84, thereby resulting in a low voltage resistance. Further, conductive dust may enter the void and remain therein during one of the intermediate steps, which also causes a decrease in voltage resistance. Conductive dust includes a photo-resist, a byproduct produced during etching of silicon, water content used during a washing process and the like. When a gate voltage is applied, a comparatively strong electric field is generated in the vicinity of the end of the gate electrode 84. Thus, apart from a device with a low operating voltage such as a memory or a logical circuit, if the semiconductor device is used in a power system, dielectric breakdown may occur between the end portion of the gate electrode 84 and the semiconductor substrate 80.
To deal with the problem of decrease in voltage resistance, it has been considered to leave a certain width 91 of gate insulation film 85 protruding from the end portion of the gate electrode 84 (See FIG. 12). However, this requires using a photomask to leave the gate insulation film 85 of the width 91 and additional steps to remove the photomask after etching, which causes a problem of an increase in costs and the time required to produce the semiconductor device.
Further, if the aforementioned step (d) of ion implantation is carried out using an ion of a relatively large atomic diameter such as arsenic, the ion does not sufficiently permeate into an oxide film. Thus, the portion of the semiconductor substrate 80 having the width 91 cannot be implanted with a sufficient amount of the ion. To form such a well structure as to provide the elements with suitable characteristics, it is necessary to control the width 91 (about 0.5 .mu.m) and the related alignment with absolute precision. However, conventional photolithography apparatus provides an insufficient alignment precision of about 0.2 .mu.m. Therefore, there is a difference in the width 91 generated between the left and right elements in FIG. 10 and the characteristics of the elements cannot be maintained uniform, thereby causing a decrease in yield.
Another approach to the problem of decrease in voltage resistance is disclosed in Japanese Patent Application Laid-Open No. HEI 7-335874. A side wall (spacer) is formed beside a gate electrode by CVD and ion implantation is carried out to form a well structure using the side wall as a mask. However, in this case, the thickness of the side wall deposited by CVD differs among or inside wafers. Hence, it is difficult to keep the characteristics of the elements uniformity, which decreases yield. The deposition layer formed by CVD or the like is not necessarily high in dielectric strength because the layer has a void at an interface between the deposition layer and the gate electrode or because the deposited substance itself contains dust or small-size lumps.